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    <title>SIMPLIS 中文討論區 - SIMPLIS 問題討論</title>
    <link>https://www.youshang.yidas.net/forum.php?mod=forumdisplay&amp;fid=37</link>
    <description>Latest 20 threads of SIMPLIS 問題討論</description>
    <copyright>Copyright(C) SIMPLIS 中文討論區</copyright>
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      <title>SIMPLIS 中文討論區</title>
      <link>https://www.youshang.yidas.net/</link>
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    <item>
      <title>在simplis中如何实现模拟信号的延时</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=560</link>
      <description><![CDATA[在cadence virtuoso中可以调用analogLib的delay模块实现模拟信号的延时，在simplis中如何实现]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>oukai</author>
      <pubDate>Mon, 09 Mar 2026 08:48:26 +0000</pubDate>
    </item>
    <item>
      <title>SIMPLIS 模擬教學文章</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=558</link>
      <description><![CDATA[https://vocus.cc/article/68f8e999fd89780001502934]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>Jeff</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202506/29/232239njvotvd87jpa1qd0.png" length="228663" type="image/jpeg" />      <pubDate>Sat, 21 Jun 2025 16:35:25 +0000</pubDate>
    </item>
    <item>
      <title>Simulator error</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=554</link>
      <description><![CDATA[Errors found during the run. Simulation aborted design.net (80):  ...
*** ERROR *** Duplicate nodes in sub-circuit definition
怎么解决？]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>xz_one</author>
      <pubDate>Tue, 11 Feb 2025 03:36:20 +0000</pubDate>
    </item>
    <item>
      <title>SIMPLIS LISN模型</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=553</link>
      <description><![CDATA[你好，請問線上研討會(https://www.youtube.com/watch?v=wO-iRHbGFf8&amp;ab_channel=simplistech) 裡面提到的LISN Model是否是在Ver 9.2之後才會有這個功能呢?]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>xyz</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202501/15/001223ijhkv9vf7bobkhou.png" length="135091" type="image/jpeg" />      <pubDate>Tue, 14 Jan 2025 16:13:01 +0000</pubDate>
    </item>
    <item>
      <title>如何增加SIMetrix模擬精度</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=542</link>
      <description><![CDATA[請問可以透過那些設定來改善SIMetrix的精細度?
我們想要透過simetrix來觀察電路的細部動作，但從波形來看卻有很多鋸齒狀，不符合現實上比較平滑的波形。 ...]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>bob_jan</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202408/12/174004jofm1xntmxsvj1vo.png" length="169298" type="image/jpeg" />      <pubDate>Mon, 12 Aug 2024 09:41:59 +0000</pubDate>
    </item>
    <item>
      <title>D型正反器結果的差異</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=522</link>
      <description><![CDATA[如附圖，在D型正反器輸入端使用Digital pulse 和waveform generator ，為什麼使用waveform generator會導致Q的結果持續維持高準位?

這邊提供模擬檔，請幫忙確認原因，謝謝




 ...]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>xyz</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202402/27/012628dqecr6zrq6orlmtb.png" length="135856" type="image/jpeg" />      <pubDate>Mon, 26 Feb 2024 17:26:38 +0000</pubDate>
    </item>
    <item>
      <title>flyback 模擬問題</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=424</link>
      <description><![CDATA[我想請問一下SIMPLIS裡面用PWL電阻模擬二極體的問題:


1.   (如附件一)為什麼需要列出逆偏的漏電流，上面漏電流是怎麼得知的?


2.    (如附件二)的TVS特別列出175和175.5V的電流差異是為什麼呢?

 ...]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>xyz</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202311/15/184325tiiii7rq5b7hl3nz.jpg" length="432217" type="image/jpeg" />      <pubDate>Wed, 15 Nov 2023 10:50:21 +0000</pubDate>
    </item>
    <item>
      <title>advanced digital logic gate有bug?</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=319</link>
      <description><![CDATA[您好，我使用advanced digital logic gate加入delay time = 50uS，跑出的結果與classic digital logic gate的行為不同。比如我用一個EN訊號，其在1.2mS時，短暫為low，再恢復為high。同時經過兩個buffer with delay time  ...]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>pilifan</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202308/31/085244pn59plv1yd077y26.jpg" length="40448" type="image/jpeg" />      <pubDate>Thu, 31 Aug 2023 00:57:05 +0000</pubDate>
    </item>
    <item>
      <title>LLC FHA gain curve詢問</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=255</link>
      <description><![CDATA[請問R1的電阻我可以設一個變數讓他從1跑到100嗎?我希望能夠一次跑完多個gain curve而不用每次設定新的R1變數就要再跑一次模擬


像附件圖片3這樣:]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>xyz</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202306/30/092845qquugexv2aauueua.png" length="52653" type="image/jpeg" />      <pubDate>Fri, 30 Jun 2023 01:32:15 +0000</pubDate>
    </item>
    <item>
      <title>Bi-directional CLLC converter CC/CV model</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=238</link>
      <description><![CDATA[我現在模擬一個infineon的CLLC電路，他的設計是CC/CV，但我目前只會用CV模式去模擬，變成我要一直去調整FB回授點以及負載電阻才能觀測到CC/CV時，電路的各個工作頻率與電壓是否正確

這邊想請問是否能提供constant current / constant voltage的模組應用範例?

infineon ...]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>xyz</author>
      <pubDate>Sat, 20 May 2023 02:21:35 +0000</pubDate>
    </item>
    <item>
      <title>flyback EMI LISN模擬問題</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=237</link>
      <description><![CDATA[最近有看到Würth Elektronik使用LTspice模擬flyback EMI的部分，由於我比較習慣使用SIMPLIS模擬，所以我轉成SIMPLIS的檔案。
Würth Elektronik研討會PDF檔案過大，所以我提供Würth Elektronik研討會的連結
https://ven ...]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>xyz</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202305/13/002209qg7131g4z0gst12l.png" length="46141" type="image/jpeg" />      <pubDate>Fri, 12 May 2023 16:23:08 +0000</pubDate>
    </item>
    <item>
      <title>開發SIMPLIS半自動化的介面</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=123</link>
      <description><![CDATA[我們想要把SIMPLIS盡量導入到案子中使用，但因為不是每個使用者都很熟悉SIMPLIS的操作，所以我們想要把幾個常用的prototype或solution做成半自動化的介面，讓使用者可以改變一部份的參數或是負載條件，就能得出新的模擬數據和報告，而使用者不必直接去操作軟體。請問類 ...]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>bob_jan</author>
      <pubDate>Wed, 20 Oct 2021 05:18:41 +0000</pubDate>
    </item>
    <item>
      <title>curve code</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=108</link>
      <description><![CDATA[Q:
Our customer would like to know if our SIMPLIS software can support the following curve code?
They tried to run the curve code, they don’t get error message, but they don’t have the result.
Therefore ...]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>youshang</author>
<enclosure url="https://www.youshang.yidas.net/data/attachment/forum/202108/16/101008r8yhbzeh12gxeehm.jpg" length="160126" type="image/jpeg" />      <pubDate>Mon, 16 Aug 2021 02:11:30 +0000</pubDate>
    </item>
    <item>
      <title>無法讀取 DIGITAL 電路</title>
      <link>https://www.youshang.yidas.net/forum.php?mod=viewthread&amp;tid=105</link>
      <description><![CDATA[Q:
讀檔後 顯示正常


F9 (run) 無法讀取 DIGITAL 電路]]></description>
      <category>SIMPLIS 問題討論</category>
      <author>youshang</author>
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